JobYooBeta
外企招聘多个职位/
2006-10-27 来自 清华大学
发信人: CrazyNash (疯狂纳什), 信区: Career_POST标 题: 外企招聘多个职位发信站: 水木社区 (Fri Oct 27 13:16:15 2006), 站内应聘
标 题: 外企招聘多个职位
发信站: 水木社区 (Fri Oct 27 13:16:15 2006), 站内
应聘条件：
以下职位相关专业博士需有1年以上工作经验，硕士需有实际工作经验2年以上，本科毕业生需三年以上工作经验方具备申请资格。
联系方式：请附简历于正文中，并在信件主题及文档首位注明所应聘的职位及编号，发送至：flutteringshadow@yahoo.com.cn
我公司为业内知名高科技企业，将为以下职位员工提供稳定可观的薪水、全面的福利和充分的成长、提升空间。还将为表现优秀的技术人员提供去美国工作和深造的机会，您将与美国硅谷专家一起从事研发工作与技术交流。
The Company Introduction:
Our Corporation is headquartered in Beijing and has several strategically subsidiaries in America Silicon Valley, Shenzhen, Shanghai and Hong Kong, Our Corporation is a world-famous multimedia CPU IC developer and provider, and also a typical high-tech corporation with wide business crossing many countries and areas.
Our Corporation is a leading semiconductor company developing and marketing embedded multimedia signal processing chips and solutions that enable multimedia applications for mobile phones over 2.5G/3G network and PCs over broadband Internet.
1.DSP Algorithm engineer
* M.S. in EE or CS, PhD preferred.
* DSP background is a must.
* 5~10+ years working experience in video signal processing, at least 3 years of TV system algorithm development.
* Proven track of record in NTSC/PAL/SECAM video decoder/encoder chip design.
* Knowledge of Macrovision, Automatic Gain Control(AGC), Genlock, Y/C separation (2D/3D comb filter), Chroma demodulation.
Quilification:
Knowledge of Closed Caption (CC), Teletext, WSS, CGMS and VBI standards.
* Fluent in Matlab, C/C++ programming is a must
* Understanding of verilog HDL programming is a plus
2. ASIC design Engineers(entry level)
-bachelor degree inElectrical/Electronics Engineering, preferably Master degree
-strong analytical abilityand problem solving skill
-familiar with Debussy, modelsim,VCS, NCVerilog, DC compiler, prime time, formality, System C etc. EDA tool.
-good at TCL/PERLscripting, C/C++, LINUX/UNIX OS
-good command in English,CET-4 certificate is a must
3. Intermediate ASIC design Engineers
- 2+ years experience with ASIC design
- Experience with logic block designs, Verilog RTL coding, synthesis and static timing analysis
- Experience creating self-checking test benches, simulations, and perform laboratory debugging
- Experience in Perl, C, Unix programming and Primetime
- Must be self-motivated and work well in a team environment and under tight deadlines
- Bachelor degree in Electrical Engineering or related field; master degree preferred
- Proficient oral and written communication skills
4. Senior ASIC design Engineers
-Master degree in Electrical/Electronics Engineering
-5+ year working experience in IC design, preferably in digital TV, set-top-box or multimedia area.
-went through at least 3IC product cycle, hand on experience in chip RTL, simulation, synthesis,
Timing closure, test bench generation at block level and chip level, strong in chip debug and bring-up
-can demonstrate leadership in the team and give technical training to junior Engineers
-expert of Debussy, modelsim, VCS, NCV erilog, DC compiler, prime time, formality, System C etc. EDA tool.
-good at TCL/PERLscripting, C/C++, LINUX/UNIX OS
-experience with XilinxFPGA prototyping and related tool(DC FPGA / synplicity / ISE ) is a plus
-good command in writtenand oral English
5.ASIC Verification Engineers
-BS/MS degree inElectronic Engineering or related field.
-2+ years ofdesign/verification experience.
-Strong understanding ofC and C++.
-Emerging verificationmethodologies would be helpful, including HVLs (SystemC, System Verilog, Vera,Verisity).
-In-depth workingknowledge of Verilog design/verification flows is mandatory.
- Proficient oral and written communication skills
6. Senior Hardware engineer
* Very familiar with TV system (LCD TV, PDP TV, PC TV, CRT P-Scan TV, RP TV or Handheld TV)
* Familiar with Layout tool
* BS or above with major in EE
* Four year+ in analog TV and/or digital TV system design
* Interested in TV hardware system design.
*Familiar with analog TV standard (NTSC/PAL/SECAM) and DVB Terrestrial/Cable/Satellite
7. Senior Layout Engineer
* Very familiar with video system layout
* Very familiar with layout tool (PADS, P-CAD, or Allegro)
* BS or Above with major in EE
* Five year+ in PCB layout
* Familiar with PCB manufacture and ROHS
* PC main board layout experience
* Familiar with PC video card (PCI, AGP, PCI-E) interface
* Good EMC and EMI reduce layout concept
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