JobYooBeta

普迪飞半导体技术（上海）有限公司招聘

2008-02-15 来自 日月光华

普迪飞半导体技术（上海）有限公司

我们的历史和使命
PDF Solutions 创立于1991年。致力于发展和利用我们独有的工艺-设计互动集成技术和服务，为IC业界提供最优的系统基础结构以提高IC良率、性能和可靠性。
总部位于美国加州的圣荷西(San Jose)，并在加州的圣地亚哥(San Diego)、德州的达拉斯(Dallas)、意大利、德国和日本拥有我们的技术中心。于2001年成为上市公司(NASDAQ: PDFS)。

我们的人才
我们现在全世界拥有近三百个超群的人才，专业领域包括工艺集成，设备物理学，TCAD，测试芯片，软件开发，集成电路设计，版图分析，数据分析，市场营销，行政和财务等诸多方面。

我们的优势
系统化的设计-工艺集成解决方案（工艺仿真软件，全面的硅性能测试芯片，系统的良率和性能增进方式方法）和卓越的咨询顾问服务能为我们的IC客户：
提高IC良率，性能和可靠性
缩短产品上市时间
短产品量产时间
提高利润

你的机遇
在PDF Solutions的杰出人才能有充分的机会去:
研发，了解全世界最尖端的半导体技术
拓展对半导体业各方面的视野
发挥创新能力，解决技术难题
积累客户服务，团队合作与领导的经验

上海分公司的使命
PDF Solutions上海分公司将成为公司的工程数据分析和标准化服务中心。我们将在超越客户对质量、服务以及效率的期待的同时，推动本公司在数据分析和方法论专长领域的进一步发展；并以此为基础，帮助拓展本公司在中国的半导体市场，从而与中国半导体客户密切合作来显著提高他们在全球市场的竞争力。

招聘职位
1. Software Development Engineer

ABOUT US:

PDF Solutions, Inc. (Nasdaq: PDFS) is a leading provider of Process-Design Int
egration technologies for integrated circuits (ICs). PDF's software, methodolo
gies and services enable semiconductor companies to create more manufacturable
 IC designs and more capable manufacturing processes. Headquartered in San Jos
e, California, PDF operates worldwide with additional offices in the US, in Eu
rope and in Asia. 
PDF Solutions works with IC manufacturers to increase yield, to accelerate yie
ld ramp and improve chip performance with the goal of reducing time-to-volume 
and time-to-market, and improving profitability. Our services and technologies
 are currently used by the majority of the top semiconductor manufacturers in 
the world. Sound interesting?

Why choose PDF?
•	Experience with state of the art semiconductor technology from fabs ar
ound the world 
•	Broad view of the semiconductor industry 
•	Opportunities to innovate and to quickly obtain responsibility 
•	High level of impact from individual contribution 
•	Working with other high caliber employees 
•	Working with ambitious, goal oriented people 
•	Exciting, challenging work environment in the silicon infrastructure s
pace 
•	Project diversity there is always something new and different to do 

•	International travel, 1-2 times a year for 1-2 weeks to the headquarte
r in San Jose 
•	Potential for personal and business growth 
•	Patent and paper recognition 
•	Competitive pay, annual bonus, stock options 
  Location:

  Shanghai, P. R. China                    

 Education:

 BS EE/CS, MS EE/CS    

 Job description: 
•	Developing and supporting a commercial yield simulation tool
•	Developing and supporting in-house tools for design, testing, and anal
ysis of Characterization Vehicle (CV)™ test chips
•	Developing and maintaining test-suites for quality assurance of the yi
eld simulation tool
•	Writing and maintaining design specification, testing specification, a
nd user’s manual
Required skills and experience:  
•	Strong C++ programming skills
•	A good understanding of object-oriented design principles and advanced
 C++ concepts
•	Excellent computer skills (UNIX/Windows) 
•	Basic UNIX shell scripting skills 
•	Excellent written and oral communication skills
•	Fluent spoken and written English
•	Self-motivated team player
Job desirables:  
•	Semiconductor/CMOS fundamentals knowledge
•	Knowledge of EDA and related programming skills
•	Experience with GUI development framework, preferably QT
•	Experience with scripting languages, such as Tcl, Perl
•	Experience with SQL and database system design
•	Experience with software testing and quality assurance
•	Familiarity with any EDA design and verification tool


2. CV Test Chip Layout Engineer
Job description: 
	Design, generate and verify specific Characterization Vehicle® test chip 
layouts to characterize clients’ manufacturing processes and quantify impact 
of design on product performance and yield. Focus on short flow (BEOL, FEOL) t
est chips. 
	Use PDF proprietary automated layout tools including layout generators, route
rs and packers to create, place and route CV test chip structures. 
	Generate all collateral needed for testing, inspection, analysis, and documen
tation of CV® Test Chips. 
	Participate with client in detailed review of test chip including post-OPC da
ta review and pre mask-making reviews 
	Work closely with PDF CV Analysis Methods to create an optimal design of expe
riments for CV® test chips. 
Required skills and experience:
	Sound understanding of semiconductor manufacturing process and transistors 

	Experience with semiconductor layout methods and layout tool suites (e.g., Ca
dence, Mentor, etc). 
	Working knowledge of DRC and LVS tools and deck creation and applicatoin 
	Basic knowledge of Unix scripting languages (e.g., perl, CSH, SH, Tcl, etc) 

	Basic knowledge of parametric test methods 
	Self-motivated and highly professional including some experience with custome
r interactions 
	Familiarity with interpreting and using Design Rule Manuals for deep sub-micr
on semiconductor processes (both foundry and IDM) 

Job desirables:
	Experience with Cadence Virtuoso and/or Cadence SKILL programming language 

	Experience with Mentor Graphics Calibre DRC
	Experience with any part of Design for Manufacturability including design mod
ification, verification, algorithms or failure analysis 
	Experience using circuit modeling software (HSPICE, Spectre, etc)
	Familiarity with semiconductor reticle-making practices (mask data prep, dumm
y fill algorithms, basics of OPC, mask fracturing and biasing, etc) 

我们注重的品格
客户至上的理念，团队精神，自强，自律，敬业。

行动起来！
让 PDF Solutions 了解您：请把您的中英文简历发送至 PDFShanghai@pdf.com
如有更多问题，人事经理 Jennifer Wang 会尽力为您解答。
电话：21-6510-1515，传真：21-6565-9016

本周招聘信息精选：

富士通2008应届毕业生校园招聘(2008-05-16)

本田（上海）招聘汽车市场调研业务人员(2008-05-16)

无印良品北京上海2008候补人才招聘(2008-05-16)

优衣库（北京、上海）店长招聘(2008-05-16)

国誉易优百销售招聘(应届生可) (2008-05-16)

本田（上海）招聘摩托车市场部品牌人员(2008-05-16)

理光公司（上海）招聘软件开发人员(2008-05-16)

*小提示：本信息由JobYoo聚合自日月光华，通过原文可了解更多信息；本信息仅供参考，请自辨真伪，并请注意有些招聘信息可能只针对信息来源院校的学生。

【我要点评】 【我要收藏】