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冠捷（上海、北京）2008校园招聘
2007-11-22 来自 清华大学
冠捷半导体（上海）有限公司及北京研发中心招聘
冠捷半导体（上海）有限公司（SST China Ltd）是注册在上海张江高科技园区内的美商独资高科技企业，主要从事集成电路及软件产品的研发、设计和测试。母公司是国际著名的半导体企业Silicon Storage Technology, Inc (SST)，成立于1989年，并于1995年在美国NASDAQ上市，是世界上主要闪存供应商之一。目前，已拥有了一批长期稳定的合作客户，如高端手持设备(Apple iPod nano播放器)，1st Silicon (Malaysia) Sdn. Bhd., Freescale Semiconductor, Inc., Grace Semiconductor Manufacturing Corporation (Grace), IBM,National Semiconductor Corporation, NEC Corporation, Samsung Electronics Co. Ltd., SANYO Semiconductor Co., Ltd., Seiko Epson Corp., Shanghai Hua Hong NEC Electronics Co., Ltd., Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), Toshiba Corporation,等。
SST入驻中国六年，正处于快速增长期，我们渴望追求卓越，致力于半导体行业的优秀人才加入；同时为您提供广阔的发展空间和畅通的晋升管道，具有竞争力的薪资、福利、津贴及假期。鲜亮的职场人生从这里起步，欢迎您的加入！
１．Digital Design Engineer（北京及上海均开放此职位）
Key Competency Requirements:
-Knowledge of non-volatile memory and architecture is a definite advantage;
-Knowledge of circuit design and verification is a definite advantage;
-Tools used may include Verilog, HSPICE/HSIM, Cadence Design Entry, Synopsis synthesis tools, P&R tools, IC layout tools, or other equivalent tools.
２．Analog Design Engineer（北京及上海均开放此职位）
Key Competency Requirements:
-Knowledge of non-volatile memory, analog designs, noise analysis, low power，leakage, high-speed memory design a definite advantage;
-Tools used may include HSPICE/HSIM, Cadence Design Entry, IC layout tools, or other equivalent tools.
３．Circuit Design Engineer（北京及上海均开放此职位）
Key Competency Requirements:
-Knowledge of CMOS full custom circuit design approach in high speed/ low power applications
-Proficiency in EDA tools like Cadence Design Entry and Layout tools, Verilog, HSPICE, nanosim, hsim, Calibre, Hercules or other equivalent tools.
-Fluent in written and conversational English.
-Knowledge of device physics and/or non-volatile memory a plus.
-Knowledge of FPGA application a plus.
４．Software Development Engineer（北京及上海均开放此职位）
Key Competency Requirements:
-Experience in EDA software development with good understanding in algorithms used in technology mapping, placement, routing, timing models or analysis;
-Excellent programming skills in C++;
-Familiar with shell scripts, Perl and/or Tcl;
-Fluent in written and conversational English.
-Knowledge of FPGA application a plus.
５．Layout Design Engineer（北京及上海均开放此职位）
Key Competency Requirements:
-Familiar with using Cadence Design Environment.
-Understanding of basic CMO design and process is a must.
６．Device Engineer（仅限上海开放）
Key Competency Requirements:
-Background in device physics of CMO/Flash/EEPROM, process technology, reliability analysis, and statistics.
- Extensive hands-on experience with at least two of the following areas: device characterization, IBasic programming, TCAD simulation and SPICE modeling.
７．Process Development Engineer（仅限上海开放）
Key Competency Requirements:
-Background in device physics of CMO/Flash/EEPROM, process technology, reliability analysis, and statistics.
-Extensive hands-on experience with at least two of the following areas: device characterization, IBasic programming, TCAD simulation and SPICE modeling.
应届毕业生应聘投递简历至hrchina@sst.com（请在邮标题中注明应聘职位、职位所在地及信息来源；请勿同时投递多个职位；请勿重复投递）。本周招聘信息精选：
*小提示：本信息由JobYoo聚合自清华大学，通过原文可了解更多信息；本信息仅供参考，请自辨真伪，并请注意有些招聘信息可能只针对信息来源院校的学生。