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Cadence Design Systems(北京、上海)校园招聘
2007-11-15 来自 chinahr
上海
Cadence Design Systems作为电子设计自动化技术的业界领导者，不断推出电子设计自动化的尖端科技，携手客户在先进芯片及系统设计中迎接挑战。Cadence上海研发中心是Cadence全球最具成长性的研发中心，承担数字芯片设计，系统设计等各方面先进电子设计自动化工具的研发任务。我们年轻而充满激情的研发团队，在实现个人技术事业飞跃的同时为公司和业界创造突破性的电子设计软件。此刻,我们正期盼同样年轻而蓬勃向上的你们加入我们的团队, 让我们共同努力,共同成长！
北京
Cadence北京研发中心位于北京海淀区知春路27号大运村量子芯座6层，承担协同美国总部共同研发Virtuoso全定制设计平台及其多模式仿真(multi-mode simulation)产品的任务。
Virtuoso 全定制设计平台是用于快速、硅精度设计的综合系统。Virtuoso平台包括：业界唯一的规格驱动的环境；使用通用语法、模型和方程式的多模式仿真；快速版图设计，用于0.18微米以下工艺的先进硅分析和全芯片混合信号集成仿真环境。使用该平台，设计团队可以用从1微米到45纳米的工艺迅速、准确、按时地设计出硅片。
我们年轻而充满激情的研发团队，在实现个人技术事业飞跃的同时为公司和业界创造突破性的电子设计软件。此刻,我们正期盼同样年轻而蓬勃向上的你们加入我们的团队, 让我们共同努力、共同成长
校园招聘职位：
Sr. PV Engineer (上海)
Responsibility:
Validate EDA software in ASIC design flow;
Responsible for developing, applying, and maintaining quality standards for complex EDA software system;
Develops and executes EDA software test plans;
Analyzes and writes test standards and procedures;
In charge of Customer Acceptance Test.
Requirement:
BS in CS/EE or similar level of expertise;
Skilled in C programming, familiar with development under Linux/Unix environment;
Better has experience of using SKILL (Cadence programming language);
Be familiar with circuit design is a plus;
Good English communication skill (both oral and writing).
Member of Technical Staff for ICD SVP development (上海)
Responsibility:
Validate EDA software in ASIC design flow;
Responsible for developing, applying, and maintaining quality standards for complex EDA software system;
Develops and executes EDA software test plans;
Analyzes and writes test standards and procedures;
In charge of Customer Acceptance Test.
Requirement:
BS in CS/EE or similar level of expertise;
Skilled in C programming, familiar with development under Linux/Unix environment;
Better has experience of using SKILL (Cadence programming language);
Be familiar with circuit design is a plus;
Good English communication skill (both oral and writing).
Substrate Noise (上海)
Responsibility:
Position 1:
This position is for a R&D engineer to assist in development of substrate noise prototyping solution in Encounter;
The candidate will be responsible for designing, developing, troubleshooting and debugging software programs in substrate noise modeling and related algorithms;
The candidate should have knowledge of semiconductor process, device models and linear system solvers.
Position 2:
This position is for a R&D engineer to assist in the development of substrate noise prototyping solution in Encounter;
The candidate will be responsible for designing, developing, troubleshooting and debugging software programs in substrate noise prototyping flow including power mode aware noise analysis and frequency analysis;
This candidate should have knowledge of digital/analog circuit.
Requirement:
Position 1:
The candidate must be proficient in C/C++ and possess good communication skills;
Minimum education requirements: Ph.D in EE or related fields.
Position 2:
The candidate must be proficient in C/C++ and possess good communication skills;
Minimum education requirements: Ph.D in EE or related fields.
Product Engineer - Encounter (上海)
Responsibility:
Position 1:
This position is for a R&D engineer to assist in development of substrate noise prototyping solution in Encounter;
The candidate will be responsible for designing, developing, troubleshooting and debugging software programs in substrate noise modeling and related algorithms;
The candidate should have knowledge of semiconductor process, device models and linear system solvers.
Position 2:
This position is for a R&D engineer to assist in the development of substrate noise prototyping solution in Encounter;
The candidate will be responsible for designing, developing, troubleshooting and debugging software programs in substrate noise prototyping flow including power mode aware noise analysis and frequency analysis;
This candidate should have knowledge of digital/analog circuit.
Requirement:
Position 1:
The candidate must be proficient in C/C++ and possess good communication skills;
Minimum education requirements: Ph.D in EE or related fields.
Position 2:
The candidate must be proficient in C/C++ and possess good communication skills;
Minimum education requirements: Ph.D in EE or related fields.
PDK Designer (Shanghai VCAD) (上海)
Responsibility:
The candidate will be responsible for the maintenance and development of the graphical interface (GUI) of Cadence circuit simulator.
The candidate must have a clear picture on Cadence circuit simulator, from its features to syntax.
Requirement:
BS in CS/EE or similar level
Skilled in C programming, familiar with development under Linux/Unix environment.
Better has experience of using SKILL (Cadence programming language).
Be familiar with circuit design is a plus.
Good English communication skill (both oral and writing).
Analog IC design engineer (Shanghai VCAD) (上海)
Responsibility:
The candidate will be responsible for the development and maintenance of the graphical user interface (GUI) of products in Encounter platform of Cadence.
Requirement:
MS/BS in CS/EE/Math.
Be Familiar with programming on Linux/Unix platform.
Be Familiar with C/C++ language.
Be Familiar with GUI application development, such as Open GL, Qt, tcl/tk, X.
EDA software development experience is a plus.
Good English communication skill, both oral and written.
Member of Technical Staff for simulator GUI development (Shanghai R&D) (上海)
Responsibility:
The candidate will be responsible for the maintenance and development of the graphical interface (GUI) of Cadence circuit simulator.
The candidate must have a clear picture on Cadence circuit simulator, from its features to syntax.
Requirement:
BS in CS/EE or similar level
Skilled in C programming, familiar with development under Linux/Unix environment.
Better has experience of using SKILL (Cadence programming language).
Be familiar with circuit design is a plus.
Good English communication skill (both oral and writing).
Member of Technical Staff (GUI development for Encounter platform) (Shanghai R&D) (上海)
Responsibility:
The candidate will be responsible for the development and maintenance of the graphical user interface (GUI) of products in Encounter platform of Cadence.
Requirement:
- MS/BS in CS/EE/Math.
- Be Familiar with programming on Linux/Unix platform.
- Be Familiar with C/C++ language.
- Be Familiar with GUI application development, such as Open GL, Qt, tcl/tk, X.
- EDA software development experience is a plus.
- Good English communication skill, both oral and written.
Senior Product Validation Engineer (Beijing R&D) (北京)
Responsibilities:
Plan and develop strategy to test Virtuoso Spectre Circuit Simulator.
Develop procedures, testcases, and designs to test, troubleshoot, and debug Virtuoso Spectre to make sure the product is performing up to the specifications and upholding software quality standards.
Work closely with a group of professionals in R&D team, PE team, and Software Release team to enhance the quality of the product.
Develop Perl scripts or shell scripts to automate test process.
Requirements:
MS or above majored in EE or CS.
Strong background in analog circuit design. Familiar with Virtuoso Spectre Circuit Simulator or other commercial circuit simulators.
Teamwork and good communication skills.
Good at both written and spoken English.
Software Quality Assurance (SQA) experience is a big plus.
Programming experience in Perl or shell script is a big plus.
Sr. R&D Position in RF/EM SOLVER (Beijing R&D) (北京)
Responsibilities:
The position is for EDA software development engineer responsible for designing, implementing and maintaining Cadence RF and high-speed circuit simulator, SpectreRF.
The engineer will be responsible for supporting development efforts through the development process, including writing specifications based on marketing and product requirements, designing and implementing product improvements and fixes.
Candidate may need to work with other global R&D teams.
Requirements:
Education Requirement: PhD in EE/CS/related research area.
Strong background in numerical computation and programming.
Hands-on experience in programming with C/C++.
Working experience in RFIC/Macrowave or in related EDA industry is big plus. Background in EE knowledge is plus.
Good command in written and oral English.
Member of technique stuff for AMS simulator development (Beijing R&D) (北京)
Responsibilities:
Develop, enhance and maintain mixed signal circuit simulator which support Verilog, Verilog-A, Verilog-AMS, VHDL, VHDL-AMS and SystemVerilog.
Requirements:
Familiar with Spice, Verilog, Verilog-A, Verilog-AMS, VHDL-AMS language
Skilled in C++ programming, familiar with development under Linux/Unix environment.
Analog circuit or digital simulator development experiences
Be familiar with Analog Mixed-signal design is a plus
EE or CS Master degree with at least 2 years related working experience or above
Product Engineer-AMS Simulator (Beijing R&D) (北京)
Responsibilities:
We are looking for a dynamic individual to join the AMS development group. The AMS group has built the exiting technology of the next generation AMS simulator. Sales are expected to grow significantly over the next years. The AMS development team is currently focused on optimizing the technology as well as on integrating the tool into the Cadence design flow. As product engineer you will shape our product and contribute to our market success.
The product engineering team is the "voice of the customer" within the AMS R&D group. It is responsible for the communication between R&D and sales, marketing, application engineering, and customers, supports customer evaluations and product roll-out, is debugging customer simulation problems, defines specifications for new simulation features and bug fixes, works together with R&D on implementation and test, maintains the customer test case suite, and is responsible for product documentation, demonstrations and trainings, as well as technical and white papers.
Requirements:
Education Requirement: MS or above in Microelectronics or related fields
Familiar with Spice, Verilog, Verilog-A, Verilog-AMS language
Analog and/or digital design experiences
Member of technique stuff for Parser development (Beijing R&D) (北京)
Responsibilities:
Develop, enhance and maintain front end parser and database for circuit simulator
Requirements:
Knowledgeable at principles of compiler,
Familiar with Lex/yacc or other lexical/syntax analyzers
Skilled in C++ programming,
Good background with development under Linux/Unix environment.
Familiarity with Spice netlist format, Clearcase, software architecture and design specifications would be a good advantage.
Circuit simulation knowledge will be a plus.
EDA experience would be desirable but not absolute requirement.
CS or EE Masters degree or above
Member of technique stuff for Fast-spice simulator (Beijing R&D) (北京)
Responsibilities:
Lead, develop, enhance and maintain fast spice simulator(ultrasim) development.
Work on complex problems where analysis of situations or data requires an in-depth evaluation of various factors.
Exercises judgment within broadly defined practices and policies in selecting methods, techniques, and evaluation criteria for obtaining results.
Requirements:
Must have a solid knowledge of analog mixed signal integrated circuit design. Knowledge on semiconductor device is strong plus
Must have deep understanding of numerical methods, particularly algorithms for ODE, nonlinear equations and matrix and is expected to have a leadership role in contributing simulation algorithm and architecting.
Must be proficient with Unix software development, ClearCase, script language, software engineering process and project management
Must be skilled in C++ programming, familiar with development under Linux/Unix environment.
Good English communication skill both verbally and in writing
EE or CS or mathematics Ph.D. degree
Device Model Software Engineer (Beijing R&D) (北京)
Responsibilities:
We are looking for highly motivated software engineer to work on SPICE compact model implementation in Cadence state-of-art simulation and modeling products.
Candidate will be responsible for novel device model research and commercial model implementation and enhancement.
Candidate may need to work with other global R&D teams and provide technical support world-wide.
Requirements
Education Requirement: MS or PhD in Microelectronics/Computer Science/Physics or related fields.
Programming with C/C++ is strongly required.
Background in device physics or device modeling is a big plus.
Experience of working on EDA products is a big plus.
Good command in written and oral English is required.
Verilog-A simulator(Beijing R&D) (北京)
Job Description:
Develop, enhance and maintain Verilog-A simulator.
Requirements:
Familiar with Spice, Verilog-A, Verilog-AMS language
Skilled in C++ programming, familiar with development under Linux/Unix environment.
Analog circuit or digital simulator development experiences.
Well understanding on circuit simulation technology, including MNA, dc, tran method.
Good mathmatic background & knowledge.
Be familiar with Analog Mixed-signal design is a plus
EE or CS Master degree with at least 2 years related working experience or above
校园宣讲会：
城市 学校 日期 时间 场地
北京 清华大学 2007-11-20 19:00-21:00 就业指导中心报告厅 （I）
上海 上海交通大学 2007-11-21 14:00-17:00 交大闵行校区电院群楼5号楼100号
复旦大学 2007-12-11 15:30-17:30 叶耀珍楼102
复旦大学微电子 2007-12-04 待定 待定
更多信息及职位申请：http://campus.chinahr.com/2008/pages/Cadence/openings.asp
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